1. Field of the Invention
The present invention relates to electronic design automation (EDA), and to implementation of changes for elements of integrated circuit designs for performance optimization.
2. Description of Related Art
Integrated circuit design is supported by electronic design automation. One approach to EDA supported design is based on the definition of an integrated circuit using a computer system as a netlist of circuit elements. Also, a cell library is provided for a given technology that includes a cells that can be chosen for use in a physical implementation of the circuit elements in the netlist. The cell library has a finite number of choices for the circuit elements, as each cell in the library is pre-qualified for manufacturability and other factors. To implement the netlist, cells are selected from the library, placed in a layout space, and interconnections are defined among the cells. The selection of cells, placement of cells and defining interconnections among the cells can be referred to as placement and routing. The result is a layout file which specifies the shapes and locations of components of the cells, and the interconnections of the cells which are to be made into an integrated circuit in a foundry.
It has been shown that small layout changes, such as transistor gate length increases, can be used to optimize integrated circuits for performance, leakage power, etc. (See, Clark, et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design,” In Proc. ISLPED (Newport, Calif., Aug. 9-11, 2004), 274-279).
Transistors with above-nominal gate lengths have been proposed and used in VLSI designs to reduce the active mode leakage power (i.e., runtime leakage). See, Puneet Gupta et al. “Selective gate-length biasing for cost-effective runtime leakage control,” Proceedings of the 41st Design Automation Conference, 2004 (Gupta 1); Shekhar Borkar et al., “Parameter variations and impact on circuits and microarchitecture” Proceeding of the Design Automation Conference, 2-6 Jun. 2003; Qian Ying Tang, et al. “Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization,” ISQED 2009, Quality of Electronic Design, 16-18 Mar. 2009; and Puneet Gupta et al., “Gate-length biasing for runtime-leakage control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, Issue 8, August 2006 (Gupta 2).
Gate length biasing can be implemented either on the cell level or on the transistor level. See, Tang; Gupta 2; Saumil Shah, et al., “Standard cell library optimization for leakage reduction,” Design Automation Conference, 2006 43rd ACM/IEEE; and Lawrence T. Clark et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design,” ISLPED 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004. The resulting lower-performance, lower-leakage standard cell variants are then exploited to replace as many cell instances as possible on design paths with positive timing slack (Gupta 2).
The value(s) of the gate length bias are usually chosen to ensure footprint equivalence and complete interchangeability between cell masters and cell variants, and the number of allowable biases may vary. For example, the dual-gate-length (DGL) approach allows the nominal gate length and one bias only. The multi-gate-length (MGL) technique, however, can use many bias values with fine increments on the cell level. MGL, similar to the within-cell transistor-level biasing, results in finer levels of granularity in delay-leakage trade-off on the cell level. Intuitively, finer levels of granularity could translate into better leakage reduction on the design level, in part by moving timing paths closer to the guard-banded zero slack timing point. Previous studies, however, reported inconsistent findings, with some showing noticeable additional leakage reduction and others observing very little advantage by using finer levels of granularity.
Procedures used to implement these small changes can be very expensive, in terms of computing resources and time required to carry them out. Also, the procedures applied to optimize circuit designs using these techniques can achieve improvements only in some circuit designs. So, the decision to implement these modification procedures to optimize a circuit characteristic can cost substantial delay and computing resources, while yielding benefits in only some cases. Also, making a best choice between alternative modification procedures can result in substantial savings in the design process.
It is desirable therefore to provide design automation tools that enable designers to predict the benefits of applying constrained optimization procedures, before committing expensive resources to carrying them out.